 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4011UB gates Quadruple 2-input NAND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 2-input NAND gate DESCRIPTION The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. HEF4011UB gates Fig.2 Pinning diagram. HEF4011UBP(N): Fig.1 Functional diagram. HEF4011UBD(F): HEF4011UBT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Schematic diagram (one gate). The splitting-up of the n-transistors provide identical inputs. FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages January 1995 2 Philips Semiconductors Product specification Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW LOW to HIGH Input capacitance 10 15 5 10 15 5 10 15 CIN tTLH tTHL tPLH tPHL 60 25 20 35 20 17 75 30 20 60 30 20 120 50 40 70 40 35 150 60 40 110 60 40 10 ns ns ns ns ns ns ns ns ns ns ns ns pF SYMBOL TYP. MAX. HEF4011UB gates TYPICAL EXTRAPOLATION FORMULA 25 ns + (0,70 ns/pF) CL 12 ns + (0,27 ns/pF) CL 10 ns + (0,20 ns/pF) CL 8 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 9 ns + (0,16 ns/pF) CL 15 ns + (1,20 ns/pF) CL 6 ns + (0,48 ns/pF) CL 4 ns + (0,32 ns/pF) CL 10 ns + (1,00 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 500 fi + (foCL) x VDD2 5 000 fi + (foCL) x VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) 25 000 fi + (foCL) x VDD2 January 1995 3 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UB gates Fig.4 Typical transfer characteristics; one input, the other input connected to VDD; VO; - - - ID (drain current); IO = 0; VDD = 5 V. Fig.5 Typical transfer characteristics; one input, the other input connected to VDD; VO; - - - ID (drain current); IO = 0; VDD = 10 V. Fig.6 Typical transfer characteristics; one input, the other input connected to VDD; VO; - - - ID (drain current); IO = 0; VDD = 15 V. January 1995 4 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UB gates Fig.7 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.8). A : average, B : average + 2 s, C : average - 2 s, where `s' is the observed standard deviation. Fig.8 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 C. January 1995 5 Philips Semiconductors Product specification Quadruple 2-input NAND gate APPLICATION INFORMATION Some examples of applications for the HEF4011UB are shown below. Because of the fact that this circuit is unbuffered, it is suitable for use in (partly) analogue circuits. HEF4011UB gates INH L H O H OSC In Fig.9 the oscillation frequency is mainly determined by R1C1, provided R1 << R2 and R2C2 << R1C1. The function of R2 is to minimize the influence of the forward voltage across the protection diodes on the frequency; C2 is a stray (parasitic) capacitance. The period Tp is given by Tp = T1 + T2, in which V DD + V ST 2V DD - V ST T 1 = R1C1 In ---------------------------and T 2 = R1C1 In ------------------------------ where V ST V DD - V ST VST is the signal threshold level of the gate. The period is fairly independent of VDD, VST and temperature. The duty factor, however, is influenced by VST. Fig.9 (a) Astable relaxation oscillator using two HEF4011UB gates; the diodes may be BAW62; C2 is a parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram. January 1995 6 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UB gates INH L H O H OSC Fig.10 Example of a crystal oscillator using one HEF4011UB gate. Fig.12 Test set-up for measuring graph of Fig.11. Condition: all other inputs connected to ground. NOTES If a gate is just used as an amplifying inverter, there are two possibilities: * Connecting the inputs together gives simpler wiring, but makes the device output not completely symmetrical. * Connecting one input to VDD will give the device a symmetrical output. Fig.11 Output voltage as a function of supply voltage. January 1995 7 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UB gates Fig.13 Voltage gain (VO/VI) as a function of supply voltage. Fig.14 Supply current as a function of supply voltage. Fig.15 Test set-up for measuring graphs of Figs 13 and 14. Condition: all other inputs connected to ground. Fig.16 Example of an analogue amplifier with inhibit using one HEF4011UB gate. January 1995 8 |
Price & Availability of HEF4011UB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |